A Semi-Floating Gate Memory with Tensile Stress for Enhanced Performance

Author:

Yuan ,Jiang ,Sun ,Chen ,Zhu ,Sun ,Zhang

Abstract

With the continuous scaling down of devices, traditional one-transistor one-capacitor dynamic random access memory (1T-1C DRAM) has encountered great challenges originated from the large-volume capacitor and high leakage current. A semi-floating gate transistor has been proposed as a capacitor-less memory with ultrafast speed and silicon-compatible technology. In this work, a U-shaped semi-floating gate memory with strain technology has been demonstrated through TCAD simulation. Ultra-high operation speed on a timescale of 5 ns at low operation voltages (≤ 2.0 V) has been obtained. And the tensile stress induced in its channel region by using contact etch stop layer (Si3N4 capper layer) was found to significantly improve the drain current by 12.07%. Furthermore, this device demonstrated a favorable retention performance with a retention time over 1 s, and its immunity to disturbance from bit-line has also been investigated that could maintain data under the continuous worst writing disturbance operation over 10 ms.

Funder

02 State Key Project

National Natural Science Foundation of China

Publisher

MDPI AG

Subject

Electrical and Electronic Engineering,Computer Networks and Communications,Hardware and Architecture,Signal Processing,Control and Systems Engineering

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