Affiliation:
1. Chair of Computer Architecture, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), 91058 Erlangen, Germany
2. NaMLab gGmbH, 01187 Dresden, Germany
Abstract
Computing systems are becoming more and more power-constrained due to unconventional computing requirements like computing on the edge, in-sensor, or simply an insufficient battery. Emerging Non-Volatile Memories are explored to build low-power computing circuits, and adders are one among them. In this work, we propose a low-power adder using a Ferroelectric Tunnel Junction (FTJ). FTJs are two-terminal devices where the data is stored in the polarization state of the device. An FTJ-based majority gate is proposed, which uses a current-mode sensing technique to evaluate the majority of the inputs. By conditionally selecting between the majority and its complement, an XOR operation is implemented, thereby achieving full-adder functionality. Since FTJ-based majority operation is slow, a ternary adder architecture is used to compensate for the speed loss. The ternary adder proposed by us has two stages of full adder and requires O(1) time for n-bit addition. The proposed adder is verified using a simulation in CMOS 130 nm technology. A 32-bit addition can be achieved in 100 μs and consumes 0.78 pJ, which is very power efficient (7.8 nW). The proposed adder can be used in applications where power consumption is crucial, and speed is not a strict requirement.
Funder
Deutsche Forschungsgemeinschaft
Deutsche Forschungsgemeinschaft and Friedrich-Alexander-Universität Erlangen-Nürnberg
Open Access Publication Funding
Subject
Electrical and Electronic Engineering,Computer Networks and Communications,Hardware and Architecture,Signal Processing,Control and Systems Engineering
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1. Hyper Dimensional Computing with Ferroelectric Tunneling Junctions;Proceedings of the 18th ACM International Symposium on Nanoscale Architectures;2023-12-18
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