Affiliation:
1. Institute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029, China
2. School of Microelectronics, University of Chinese Academy of Sciences, Beijing 100049, China
3. CASEMIC Electronics Technology Co., Ltd., Hangzhou 310051, China
Abstract
The QC-LDPC code, with its excellent error correction performance and hardware friendliness, has been identified as one of the channel encoding schemes by Wi-Fi 6. Shorting, puncturing, or repeating operations are needed to ensure that user data can be sent with integer symbols and complete rate matching. Due to the uncertainty of the user data size, the modulation’s selectivity, and the difference in the number of spatial streams, the receiver must deal with more than 106 situations. At the same time, other computationally intensive tasks occupy the time slot budget of the receiver. Typical are demodulation and decoding. Hence, the receiver needs to quickly reverse the demodulated data process. This paper first proposes a co-processing method and VLSI architecture compatible with all code lengths, code rates, and processing parameters. The co-processor separates field and block splicing, simplifying the control logic. There is no throughput rate bottleneck, and the maximum delay is less than 1 us.
Subject
Electrical and Electronic Engineering,Computer Networks and Communications,Hardware and Architecture,Signal Processing,Control and Systems Engineering
Reference10 articles.
1. (2016). Standard No. IEEE, 802.11-2016.
2. (2021). Standard No. IEEE, 802.11ax-2021.
3. (2004). Standard No. IEEE, 802.16-2004.
4. (2020). Standard No. 3GPP TS 38.212 V16.1.0 (2020–03).
5. Error Performance Prediction of Randomly Shortened and Punctured LDPC Codes;Suls;IEEE Commun. Lett.,2019
Cited by
1 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献