Programmable Deterministic Zero-Copy DMA Mechanism for FPGA Accelerator

Abstract

With the expansion of network scales, the B/S architecture of monolithic applications is gradually being replaced by microservices. The unbundling of services has led to exponential growth in the size of APIs. When handling massive microservice requests, the commercial NIC shows limitations in three aspects: deterministic, programmability, and data copy. To ensure that each microservice node handles requests efficiently, flexibly, and precisely, this paper proposes a programmable deterministic multi-queue FPGA Accelerator. The Accelerator relies on the instantiated 1000 queues and the queue management unit to extend the rule-based RSS algorithm for the serverless-friendly programmability of packet distribution. A PTP hardware clock is added to collaborate with the queue management unit to control the deterministic delivery. To improve the sending and receiving efficiency of network node data, a driver adapted to the FPGA accelerator is designed to realize zero-copy. Experiments conducted on a 100 Gbps FPGA show that the Accelerator can support the multi-queue transmission with various packet sizes, define the forwarding behavior, and almost approach the line rate on an 8-core FPGA device. In addition, it can forward packets with low latency close to that of the current state-of-the-art ovs-DPDK. This Accelerator overcomes, to some extent, the limitations of commercial NICs when oriented to microservice architectures.