Affiliation:
1. École de Technologie Supérieure (ÉTS), Montreal, QC H3C 1K3, Canada
Abstract
A wideband cascaded receiver and a stacked receiver using an improved clock strategy are proposed to support the software-defined radio (SDR). The improved clock strategy reduces the number of mixer switches and the number of LO clock paths required to drive the mixer switches. This reduces the dynamic power consumption. The cascaded receiver includes an inverter-based low-noise transconductance amplifier (LNTA) using a feed-forward technique to enhance the noise performance; a passive mixer; and an inverter-based transimpedance amplifier (TIA). The stacked receiver architecture is used to reduce the power consumption by sharing the current between the LNTA and the TIA from a single supply. It utilizes a wideband LNTA with a capacitor cross-coupled (CCC) common-gate (CG) topology, a passive mixer to convert the RF current to an IF current, an active inductor (AI) and a 1/f noise-cancellation (NC) technique to improve the noise performance, and a TIA to convert the IF current to an IF voltage at the output. Both cascaded and stacked receivers are simulated in 22 nm CMOS technology. The cascaded receiver achieves a conversion-gain from 26 dB to 36 dB, a double-sideband noise-figure (NFDSB) from 1.4 dB to 3.9 dB, S11<−10 dB and an IIP3 from −7.5 dBm to −10.5 dBm, over the RF operating band from 0.4 GHz to 12 GHz. The stacked receiver achieves a conversion-gain from 34.5 dB to 36 dB, a NFDSB from 4.6 dB to 6.2 dB, S11<−10 dB, and an IIP3 from −21 dBm to −17.5 dBm, over the RF operating band from 2.2 GHz to 3.2 GHz. The cascaded receiver consumes 11 m from a 1 V supply voltage, while the stacked receiver consumes 2.4 m from a 1.2 V supply voltage.
Funder
Natural Sciences and Engineering Research Council of Canada
Subject
Electrical and Electronic Engineering
Reference24 articles.
1. The software radio architecture;Mitola;IEEE Commun. Mag.,1995
2. Ke, Y., Gao, P., Craninckx, J., Van der Plas, G., and Gielen, G. (2020, January 16–18). A 2.8-to-8.5 mW GSM/bluetooth/UMTS/DVB-H/WLAN fully reconfigurable CT ΔΣ with 200kHz to 20MHz BW for 4G radios in 90nm digital CMOS. Proceedings of the 2010 Symposium on VLSI Circuits, Honolulu, HI, USA.
3. A noise-cancelling receiver resilient to large harmonic blockers;Murphy;IEEE J. -Solid-State Circuits,2015
4. An RF-to-BB-current-reuse wideband receiver with parallel N-path active/passive mixers and a single-MOS pole-zero LPF;Lin;IEEE J. -Solid-State Circuits,2014
5. A wideband receiver front-end using 1st and 3rd harmonics of the N-path filter response;Elmi;Analog. Integr. Circuits Signal Process.,2018
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