Barrier Height, Ideality Factor and Role of Inhomogeneities at the AlGaN/GaN Interface in GaN Nanowire Wrap-Gate Transistor

Author:

Mallem Siva Pratap Reddy1,Puneetha Peddathimula2,Choi Yeojin3,Baek Seung Mun3ORCID,Lee Dong-Yeon2,Im Ki-Sik4,An Sung Jin3ORCID

Affiliation:

1. Advanced Material Research Center, Kumoh National Institute of Technology, Gumi 39177, Republic of Korea

2. Department of Robotics and Intelligent Machine Engineering, College of Mechanical and IT Engineering, Yeungnam University, Gyeongsan 38541, Republic of Korea

3. Department of Materials Science and Engineering, Kumoh National Institute of Technology, Gumi 39177, Republic of Korea

4. Department of Green Semiconductor System, Daegu Campus, Korea Polytechnics, Daegu 41765, Republic of Korea

Abstract

It is essential to understand the barrier height, ideality factor, and role of inhomogeneities at the metal/semiconductor interfaces in nanowires for the development of next generation nanoscale devices. Here, we investigate the drain current (Ids)–gate voltage (Vgs) characteristics of GaN nanowire wrap-gate transistors (WGTs) for various gate potentials in the wide temperature range of 130–310 K. An anomalous reduction in the experimental barrier height and rise in the ideality factor with reducing the temperature have been perceived. It is noteworthy that the variations in barrier height and ideality factor are attributed to the spatial barrier inhomogeneities at the AlGaN/GaN interface in the GaN nanowire WGTs by assuming a double Gaussian distribution of barrier heights at 310–190 K (distribution 1) and 190–130 K (distribution 2). The standard deviation for distribution 2 is lower than that of distribution 1, which suggests that distribution 2 reflects more homogeneity at the AlGaN/GaN interface in the transistor’s source/drain regions than distribution 1.

Funder

Ministry of Education

Ministry of Education, Science and Technology

Publisher

MDPI AG

Subject

General Materials Science,General Chemical Engineering

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