Hardware-software architecture for priority queue management in real-time and embedded systems
Author:
Publisher
Inderscience Publishers
Subject
Hardware and Architecture,Software
Cited by 12 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A Fast Scalable Hardware Priority Queue and Optimizations for Multi-Pushes;2024 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW);2024-05-27
2. PeakEngine: A Deterministic On-the-Fly Pruning Neural Network Accelerator for Hearing Instruments;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-01
3. AnTiQ: A Hardware-Accelerated Priority Queue Design with Constant Time Arbitrary Element Removal;2023 26th Euromicro Conference on Digital System Design (DSD);2023-09-06
4. BMW Tree: Large-scale, High-throughput and Modular PIFO Implementation using Balanced Multi-Way Sorting Tree;Proceedings of the ACM SIGCOMM 2023 Conference;2023-09
5. A Min-Heap-Based Accelerator for Deterministic On-the-Fly Pruning in Neural Networks;2023 IEEE International Symposium on Circuits and Systems (ISCAS);2023-05-21
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