Power Limiter with PIN Diode Embedded in Cavity to Minimize Parasitic Inductance
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Published:2022-11-30
Issue:6
Volume:22
Page:686-688
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ISSN:2671-7255
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Container-title:Journal of Electromagnetic Engineering and Science
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language:en
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Short-container-title:J. Electromagn. Eng. Sci
Author:
Jung Dong Yun,Park Kun Sik,Won Jong Il,Cho Doohyung,Kwon Sungkyu,Jang Hyun Gyu,Lim Jong-Won
Abstract
This letter introduces a power limiter that limits the input power to protect the receiver when a large power enters the radio frequency receiver. When the power limiter receives a large power signal, a positive-intrinsic-negative (PIN) diode is turned on to limit the input power by lowering the impedance. We analyzed the characteristics of the power limiter according to the method of connecting the PIN diode in parallel with the input and output transmission lines of the power limiter. By embedding a PIN diode into the cavity and minimizing the length of the wire, a power limiter was designed and implemented to minimize parasitic inductance. In the S-band, the proposed power limiter’s insertion loss was below 0.5 dB, and the reflection loss characteristics were below 15 dB. Furthermore, it achieved an output P1dB of 21.8 dBm at 3.5 GHz.
Funder
CivilMilitary Technology Cooperation Program
National Research Council of Science and Technology
Ministry of Science and ICT
Publisher
Korean Institute of Electromagnetic Engineering and Science
Subject
Electrical and Electronic Engineering,Computer Networks and Communications,Instrumentation,Radiation
Cited by
1 articles.
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