A low sampling clock, high bandwidth, master‐slave track and hold amplifier

Author:

Zhang Guifu1ORCID,Zhou Jie1,Liu Youjiang1,Cao Tao1,Qiu Yongtao1,Li Biao1

Affiliation:

1. Institute of Electronic Engineering, China Academy of Engineering Physics Mianyang China

Publisher

Wiley

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Computer Science Applications

Reference24 articles.

1. A 50 GS/s distributed T/H amplifier in 0.18 μm SiGe BiCMOS;Lee J;IEEE ISSCC Dig Tech Papers,2007

2. An 8‐bit, 12 GSample/sec SiGe track‐and‐hold amplifier;Lu Y;Proc IEEE BCTM,2005

3. A broadband 10-GHz track-and-hold in Si/SiGe HBT technology

4. A 3 b 40 GS/s ADC‐DAC in 0.12 μm SiGe;Cheng W;IEEE ISSCC Dig Tech Papers,2004

5. Design Methodology for a 40-GSamples/s Track and Hold Amplifier in 0.18-$muhbox m$SiGe BiCMOS Technology

Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Research on Track/Hold Circuit Based on Feedback Compensation;2021 IEEE 16th Conference on Industrial Electronics and Applications (ICIEA);2021-08-01

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