Chip‐to‐Wafer and Wafer‐to‐Wafer Integration Schemes

Author:

Matthias Thorsten,Pargfrieder Stefan,Wimplinger Markus,Lindner Paul

Publisher

Wiley

Reference8 articles.

1. Morrow P. Kobrinsky M.J. Ramanathan S. Partk C.‐M. Harmes M. Ramachandrarao V. Park H.‐M. Kloster G. List S.andKim S.(2005)Wafer‐Level 3D Interconnects Via Cu Bonding. Proceedings of the UC Berkeley Extension Advanced Metallization Conference (AMC 2004) Mater. Res. Soc. Symp. Proc 20 p.125–130.

2. Tadepalli Rajappa.andThompson Carl V.(2003)Quantitative characterization and process optimization of low‐temperature bonded copper interconnects for 3‐D integrated circuits. Proceedings of the IEEE 2003 International Interconnect Technology Conference IEEE Catalog # 03TH8695 p.36.

3. Effects of bonding process parameters on wafer‐to‐wafer alignment accuracy in benzocyclobutene (BCB) dielectric wafer bonding;Niklaus F.;Materials Research Society Symposium Proceedings,2005

4. McMahon J.J. Lu J.‐Q.andGutmann R.J.(2005)Wafer bonding of damascene‐patterned metal/adhesive redistribution layers for via‐first three‐dimensional

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