1. Design of ion implanted MOSFET's with very small physical dimensions;Dennard;IEEE J. Solid-State Circuits,1974
2. Optimal interconnection circuits for VLSI;Bakoglu;IEEE Trans. Electron Devices,1985
3. Edelstein , D. Heidenreich , J. Goldblatt , R. Cote , W. Uzoh , C. Lustig , N. Roper , P. McDevitt , T. Motsiff , W. Simon , A. Dukovic , J. Wachnik , R. Rathore , H. Schulz , R. Su , L. Luce , L.S. Slattery , J. 1997 Full copper wiring in a sub-0.25 µm CMOS ULSI technology 773 776
4. Kikkawa , T. Chikaki , S. Yagi , R. Shimoyama , M. Shishida , M. Fujii , N. Kohmura , K. Tanaka , H. Nakayama , T. Hishiya , S. Ono , T. Yamanishi , T. Ishikawa , A. Matsuo , H. Seino , Y. Hata , N. Yoshino , T. Takada , S. Kawahara , J. Kinoshita , K. 2005 Advanced scalable ultra low- k /Cu interconnect technology for 32 nm CMOS ULSI using self-assembled porous silica and self-aligned CoWP barrier 99 102