1. Joshi , R. Klepner , S. Basavaiah , S. et al 1991 Process integration for a 2 ns cycle/4 ns access 512K CMOS SRAM 31 32
2. Kaanta , C. Cote , W. Cronin , J. et al 1998 Submicron wiring technology with tungsten and planarization 21 28
3. Doan , T. Bellersen , M. de Bruin , L. et al 1998 A double level metallization system having 2 µm pitch for both levels 13 20
4. Thomas , M.E. Sekigahama , S. Renteln , P. et al 1990 The mechanical planarization of inter-level dielectrics for multilevel interconnect applications 438 440
5. Bohr , M. Ahmed , U. Brigham , L. et al 1994 A high performance 0.35 µm logic technology for 3.3 V and 2.5 V operation 273 276