P‐5: 27‐inch Ultra‐Narrow‐Border LCD with a Two‐Stage Output Gate Driver Circuit

Abstract

A two‐stage output gate driver circuit with a clock‐controlled inverter is proposed and investigated. High and low voltage switching of inverter diminishes the positive bias stress of amorphous silicon TFTs in the circuit. The design of one cell with two‐stage output reduces the number of blocks in the gate driver circuit by half. This circuit was successfully developed for a 27‐inch LCD product with a 1.88 mm border.