1. et al. Ultra narrow trench-isolated 0.2 μm CMOS and its application to ultra low power frequency dividers. IEEE IEDM Tech. Dig., Washington, D.C., pp. 887–890 (Dec. 1993).
2. , , and . Reverse elevated source drain MOSFET for deep submicron CMOS. IEEE IEDM Tech. Dig., San Francisco, pp. 885–888 (Dec. 1992).
3. Selective Silicon Epitaxy Using Reduced Pressure Technique
4. et al. Scaled CMOS technology using SEG isolation and buried well process. IEEE Trans, on ED, pp. 1659–1665 (1986).
5. and . A submicron dual buried layer twin well CMOS SEG process. IEDM Tech. Dig., Washington, D.C., pp. 20–23 (Dec. 1987).