The optimization of a DRAM CMOS row decoder circuit-Reference-Cited by-同舟云学术

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The optimization of a DRAM CMOS row decoder circuit

Published:1990 Issue:3 Volume:73 Page:1-9
ISSN:8756-663X
Container-title:Electronics and Communications in Japan (Part II: Electronics)
language:en
Short-container-title:Electron. Comm. Jpn. Pt. II

Author:

Ozaki Hideyuki,Miyamot Hiroshi,Yamagata Tadato,Hidaka Hideto

Publisher

Wiley

Subject

Electrical and Electronic Engineering,Computer Networks and Communications,General Physics and Astronomy

Reference14 articles.

1. , , , , , , , , , , , , , and . A 4-Mb DRAM with crosspoint trench transistor cell. ISSCC Dig. Tech. Papers, pp. 268–269 (1986).

2. , , , , , , , , and . A 4-Mb DRAM with half internal-voltage bitline precharge. ISSCC Dig. Tech. Papers, pp. 270–271 (1986).

3. , , , , , , , and . An experimental 4-Mb CMOS DRAM. ISSCC Dig. Tech. Papers, pp. 272–273 (1986).

4. , , , , , , and . A 90-ns, 4-Mb DRAM in a 300-mil DIP. ISSCC Dig. Tech. Papers, pp. 12–13 (1987).

5. , , , , , , , , , , , , and . A 4-Mb DRAM with double-buffer static-column architecture. ISSCC Dig. Tech. Papers, pp. 14–15 (1987).

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 64 $\times$ 64-Pixel CMOS Test Chip for the Development of Large-Format Ultra-High-Speed Snapshot Imagers;IEEE Journal of Solid-State Circuits;2008-09

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