A 5-ns 32 K ×8/×9 bi-CMOS TTL SRAM with alternated bit line load architecture-Reference-Cited by-同舟云学术

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A 5-ns 32 K ×8/×9 bi-CMOS TTL SRAM with alternated bit line load architecture

Published:1994-02 Issue:2 Volume:77 Page:65-76
ISSN:8756-663X
Container-title:Electronics and Communications in Japan (Part II: Electronics)
language:en
Short-container-title:Electron. Comm. Jpn. Pt. II

Author:

Ohbayashi Shigeki,Shiomi Toru,Matsuo Ryuichi,Sumi Tadashi,Honda Hiroki,Ishigaki Yoshiyuki,Uga Kimiharu,Ishida Masahiro,Kohno Yoshio

Publisher

Wiley

Subject

Electrical and Electronic Engineering,Computer Networks and Communications,General Physics and Astronomy

Reference10 articles.

1. A 6-ns 256-kb BiCMOS TTL SRAM

2. , , , , , , , and . New Bit Line Architecture for Ultra-High-Speed SRAMs—T-Shaped Bit line and Its Real Application to 256-K BiCMOS TTL SRAM. Proceedings of the IEEE 1991 CICC, pp. 10.4.1–10.4.4 (May 1991).

3. , , , , , , and . Data-Line Wiring Delay Reduction Techniques for High-Speed BiCMOS SRAMs. Symposium on VLSI Circuits Digest of Technical Papers, pp. 19–20 (May 1991).

4. , , , , , , , and . A 9-ns, 4-Mb BiCMOS SRAM with 3.3-V operation. ISSCC Dig. Tech. Papers, pp. 210–211 (Feb. 1992).

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