An improved asymmetrical multilevel inverter topology with reduced semiconductor device count-Reference-Cited by-同舟云学术

An improved asymmetrical multilevel inverter topology with reduced semiconductor device count

Author:

Sarwer Zeeshan¹^ORCID,Siddique Marif Daula²^ORCID,Iqbal Atif²^ORCID,Sarwar Adil¹^ORCID,Mekhilef Saad³⁴⁵^ORCID

Affiliation:

1. Department of Electrical Engineering, Z. H. College of Engineering and Technology Aligarh Muslim University Aligarh India

2. Department of Electrical Engineering Qatar University Doha Qatar

3. Power Electronics and renewable Energy Laboratory, Department of Electrical Engineering University of Malaya Kuala Lumpur Malaysia

4. School of Software and Electrical Engineering Swinburne University of Technology Melbourne Victoria Australia

5. Center of Research Excellence in Renewable Energy and Power Systems King Abdulaziz University Jeddah Saudi Arabia

Funder

Ministry of Higher Education, Malaysia

Universiti Malaya

Publisher

Hindawi Limited

Subject

Electrical and Electronic Engineering,Energy Engineering and Power Technology,Modeling and Simulation

Link

Reference37 articles.

Cited by 35 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

4. Designing N^th Level Inverter Using Asymmetric H-bridge MLI Topology: with Techniques to Minimize THD;2024 IEEE 3rd International Conference on Control, Instrumentation, Energy & Communication (CIEC);2024-01-25