Wafer‐Scale Integration of Single Layer Graphene Electro‐Absorption Modulators in a 300 mm CMOS Pilot Line

Abstract

AbstractGraphene‐based devices have shown great promise for several applications. For graphene devices to be used in real‐world systems, it is necessary to demonstrate competitive device performance, repeatability of results, reliability, and a path to large‐scale manufacturing with high yield at low cost. Here, single‐layer graphene electro‐absorption modulators are selected as test vehicles, and their wafer‐scale integration is established in a 300 mm pilot complementary metal‐oxide–semiconductor (CMOS) foundry environment. A hardmask is used to shape graphene, while tungsten‐based contacts are fabricated using the damascene approach to enable CMOS‐compatible fabrication. By analyzing data from hundreds of devices per wafer, the impact of specific processing steps on the performance could be identified and optimized. After optimization, modulation depth of 50 ± 4 dB mm−1 is demonstrated on 400 devices measured using 6 V peak‐to‐peak voltage. The electro‐optical bandwidth is up to 15.1 ± 1.8 GHz for 25 m‐long devices. The results achieved are comparable to lab‐based record‐setting graphene devices of similar design and CVD graphene quality. By demonstrating the reproducibility of the results across hundreds of devices, this work resolves the bottleneck of graphene wafer‐scale integration. Furthermore, CMOS‐compatible processing enables co‐integration of graphene‐based devices with other photonics and electronics building blocks on the same chip for high‐volume, low‐cost manufacturing.