An efficient memory operations optimization technique for vector loops on Itanium 2 processors

Author:

Jalby William,Lemuet Christophe,Touati Sid-Ahmed-Ali

Publisher

Wiley

Subject

Computational Theory and Mathematics,Computer Networks and Communications,Computer Science Applications,Theoretical Computer Science,Software

Reference29 articles.

1. , . Parallel Computer Architecture: A Hardware/Software Approach. Morgan Kaufmann: San Francisco, CA, 1999.

2. , . How useful are non-blocking loads, stream buffers and speculative execution in multiple issue processors? Proceedings of the 1st International Symposium on High-Performance Computer Architecture, Raleigh, NC, January 1995. IEEE Computer Society: Los Alamitos, CA, 1995; 78–89.

3. Effective hardware-based data prefetching for high-performance processors

4. On the effective bandwidth of interleaved memories in vector processor systems

5. Superscalar Microprocessor Design. Prentice-Hall: Englewood Cliffs, NJ, 1991.

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1. Bibliography;Advanced Backend Code Optimization;2014-06-03

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