Reducing the burden of parallel loop schedulers for many‐core processors-Reference-Cited by-同舟云学术

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Reducing the burden of parallel loop schedulers for many‐core processors

Published:2021-04-05 Issue:13 Volume:33 Page:
ISSN:1532-0626
Container-title:Concurrency and Computation: Practice and Experience
language:en
Short-container-title:Concurrency Computat Pract Exper

Author:

Arif Mahwish¹,Vandierendonck Hans²³^ORCID

Affiliation:

1. Computer Science Laboratory University of Cambridge Cambridge UK

2. School of Electronics, Electrical Engineering and Computer Science Queen's University Belfast Belfast Northern Ireland

3. Queen's University Belfast Belfast BT7 1NN Northern Ireland

Funder

Engineering and Physical Sciences Research Council

FP7 Information and Communication Technologies

FP7 People: Marie-Curie Actions

H2020 Future and Emerging Technologies

Publisher

Wiley

Subject

Computational Theory and Mathematics,Computer Networks and Communications,Computer Science Applications,Theoretical Computer Science,Software

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1002/cpe.6241

Reference49 articles.

1. Knights Landing: Second-Generation Intel Xeon Phi Product

2. HeY LeisersonCE LeisersonWM. The cilkview scalability analyzer. Paper presented at: Proceedings of the 22nd Annual ACM Symposium on Parallelism in Algorithms and Architectures SPAA '10;2010:145‐156; ACM New York NY.

3. FrigoM LeisersonCE RandallKH. The implementation of the cilk‐5 multithreaded language. Paper presented at: Proceedings of the ACM SIGPLAN 1998 Conference on Programming Language Design and Implementation PLDI '98;1998:212‐223; ACM New York NY.

4. ShunJ BlellochGE. Ligra: a lightweight graph processing framework for shared memory. Paper presented at: Proceedings of the 18th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming PPoPP '13;2013:135‐146; ACM New York NY.

5. https://www.cilkplus.org.

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1. Accounting Start-up Time of Parallel Processes in Amdahl’s Law;Parallel Processing Letters;2021-12-13

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