A low kickback fully differential dynamic comparator for pipeline analog‐to‐digital converters-Reference-Cited by-同舟云学术

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A low kickback fully differential dynamic comparator for pipeline analog‐to‐digital converters

Published:2019-11 Issue:4 Volume:1 Page:
ISSN:2577-8196
Container-title:Engineering Reports
language:en
Short-container-title:Engineering Reports

Author:

Diaz‐Madrid Jose‐Angel¹^ORCID,Domenech‐Asensi Gines²,Hauer Johann³,Mateu Loreto³

Affiliation:

1. Departamento de Ingenieria y Tecnicas AplicadasCentro Universitario de la Defensa en San Javier Santiago de la Ribera Spain

2. Departamento de Electrónica, Tecnología de Computadoras y Proyectos Universidad Politecnica de Cartagena Cartagena Spain

3. Fraunhofer Institute for Integrated Circuits IIS Erlangen Germany

Funder

Spanish government projects

Publisher

Wiley

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1002/eng2.12055

Reference13 articles.

1. YasueT TomiokaK FunatsuR et al.A 33Mpixel CMOS imager with multi‐functional 3‐stage pipeline ADC for 480 fps high‐speed mode and 120 fps low‐noise mode. In: Proceedings of the IEEE International Solid‐State Circuits Conference;2018;San Francisco CA.

2. Low‐noise dynamic comparator circuit with selectable input‐referred thermal noise voltage

3. Kickback noise reduction techniques for CMOS latched comparators

4. DuongDV NguyenTV.A capacitive dynamic comparator with low kickback noise for pipelined ADC. Paper presented at: IEEE International Conference on Electronics Computing and Communication Technologies;2013;Bangalore India.https://doi.org/10.1109/CONECCT.2013.6469281

5. 14‐bit 100 MS/s 121 mW pipelined ADC;Yongzhen C;J Semicond,2015

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1. Design and Analysis of Low Power and High-Speed Dynamic Comparator with Transconductance Enhanced in Latching Stage for ADC Application;Journal of Circuits, Systems and Computers;2024-02-19

2. Design of a 0.4 V, 8.43 ENOB, 5.29 nW, 2 kS/s SAR ADC for Implantable Devices;Electronics;2023-11-18

3. A complementary fully differential dynamic comparator with insensitive common-mode mismatch;IEICE Electronics Express;2022-08-25

4. A complementary fully differential dynamic comparator with insensitive common-mode mismatch;IEICE ELECTRON EXPR;2022

5. A low-power 6-bit successive approximation register ADC using a new split capacitor array method;2021 IEEE Asia Pacific Conference on Circuit and Systems (APCCAS);2021-11-22

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