A method to generate formulas for temporal logic satisfiability checkers-Reference-Cited by-同舟云学术

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A method to generate formulas for temporal logic satisfiability checkers

Published:2007 Issue:11 Volume:90 Page:99-108
ISSN:8756-663X
Container-title:Electronics and Communications in Japan (Part II: Electronics)
language:en
Short-container-title:Electron. Comm. Jpn. Pt. II

Author:

Sekizawa Toshifusa,Takai Toshinori,Tanabe Yoshinori,Takahashi Koichi

Publisher

Wiley

Subject

Electrical and Electronic Engineering,Computer Networks and Communications,General Physics and Astronomy

Reference14 articles.

1. , . Model checking. MIT Press; 2000.

2. , . Patterns in property specifications for finite-state verification. Proc 21st International Conference on Software Engineering, 1999.

3. Temporal and modal logic. In: Handbook of theoretical computer science, Vol. B. Elsevier and MIT Press; 1990. p 995–1072.

4. Using branching time temporal logic to synthesize synchronization skeletons

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