Design of a 180 nm CMOS Neuron Circuit with Soft‐Reset and Underflow Allowing for Loss‐Less Hardware Spiking Neural Networks

Abstract

Spiking neural networks (SNNs) have been researched as an alternative to reduce the gap with the human brain in terms of energy efficiency, due to their inherent spare event‐driven characteristics from a hardware implementation perspective. However, they still face significant challenges in learning, compared to artificial neural networks (ANNs). Recently, several algorithms have been developed to narrow the performance gap between SNNs and ANNs, including features in spiking neurons that can reduce information loss in the membrane potential. Inspired by these advancements, the current study designs and measures a neuron circuit using 180 nm complementary metal‐oxide‐semiconductor (CMOS) technology to address this information loss. The proposed circuit successfully implements these features, and their performance is validated through simulation based on the measured data.