Affiliation:
1. Department of Electrical and Computer Engineering and Inter-university Semiconductor Research Center Seoul National University 1 Gwanak-ro, Gwanak-gu Seoul 08826 Republic of Korea
2. School of Electrical Engineering Kookmin University 77, Jeongneung-ro, Seongbuk-gu Seoul 02707 Republic of Korea
3. School of Electronics and Electrical Engineering Kyungpook National University 80 Daehakro, Bukgu Daegu 41566 Republic of Korea
Abstract
Herein, dual‐gate field‐effect transistors (DG FETs) fabricated on Si substrate and a corresponding NOR‐type array designed for low‐power on‐chip trainable hardware neural networks (HNNs) are presented. The fabricated DG FET exhibits notable endurance characteristics, with the subthreshold swing remaining consistently within a 2.45% range of change and ΔV
th per cycle maintaining stability at 4.5% over repetitive program and erase operations, up to 104 cycles. Furthermore, a multilevel characteristic is achieved through low‐power program/erase operations based on Fowler–Nordheim (FN) tunneling, which exhibit 0.09 and 0.99 fJ per spike, respectively. These characteristics provide the HNN stability, along with high performance and power efficiency. The NOR‐type array in this work demonstrates selective update and bidirectional vector‐by‐matrix multiplication capabilities. This enables on‐chip training based on a gradient descent algorithm, without the need for an additional array for backpropagation. Subsequently, a simulation of the Modified National Institute of Standards and Technology classification is conducted to evaluate the accuracy and training power consumption of the proposed device in comparison to other two‐terminal memristor devices. The results show that the DG FET array achieves superior accuracy while maintaining over 180.4 times higher energy efficiency, demonstrating the potential of the DG FET as a promising candidate for low‐power HNN applications.
Reference67 articles.
1. GPT-3: Its Nature, Scope, Limits, and Consequences
2. X.Zhou W.Gong W.Fu F.Du presented atIEEE/ACIS 16th Int. Conf. Comp. Info. Sci. Wuhan May2017.
3. A.Graves A.Mohamed G.Hinton presented atIEEE Int. Conf. Acous. Speech Signal Process. Vancouver May2013 p.6645.
4. A.Ramesh M.Pavlov G.Goh S.Gray C.Voss A.Radford M.Chen I.Sutskever presented atInt. Conf. Mach. Learning Virtual Event July2021.
5. J.Devlin M. W.Chang K.Lee K.Toutanova (preprint) arXiv:1810.04805 v2 Submitted: May2019.