Analytical modelling of ultra‐small group delay variation of ultra‐broadband RF power amplifier using NSGA‐II algorithm

Abstract

AbstractThis paper proposes a ± 9.4 ps ultra‐small group delay (GD) variation of fully integrated 65 nm complementary metal oxide semiconductor (CMOS) power amplifier (PA) over 6.5–17 GHz broadband for wireless application. The proposed CMOS PA is realised by using broadband stage, RLC inter‐stage and power stage topologies. The non‐dominated sorting genetic algorithm (NSGA‐II) is employed for PA parameter optimisation to ensure a small GD variation of ±9.4 ps over broadband with an excellent small signal gain flatness of 23.65 ± 1.85 for 6.5–17 GHz. The small GD variation of ±9.4 ps and ± 11.05 ps are attained under two cases of DC supply voltages of 2.4/1.2 V and 1.2/1.2 V, respectively. To the best of author's knowledge, the achieved GD variations are lowest among all CMOS PAs as reported so far. In addition, an analytical modelling of GD is derived to validating the minimum GD variation using zero‐pole compensation. With supply voltages of 2.4/1.2 V at 6.5 GHz, the large signal power gain, Psat and OP1dB are 26 dB, 19.3 dBm and 17.94 dBm, respectively, while peak power added efficiency (PAE) is 38.196%. At reduced supply voltages of 1.2/1.2 V, the PA achieves maximum power gain of 17.7 dB and peak PAE of 35% at 6.5 GHz. The CMOS PA occupies an area of 0.206 mm2.