An architecture for exploiting multi-core processors to parallelize network intrusion prevention-Reference-Cited by-同舟云学术

An architecture for exploiting multi-core processors to parallelize network intrusion prevention

Published:2009-07 Issue:10 Volume:21 Page:1255-1279
ISSN:1532-0626
Container-title:Concurrency and Computation: Practice and Experience
language:en
Short-container-title:Concurrency Computat.: Pract. Exper.

Author:

Sommer Robin,Paxson Vern,Weaver Nicholas

Publisher

Wiley

Subject

Computational Theory and Mathematics,Computer Networks and Communications,Computer Science Applications,Theoretical Computer Science,Software

Link

http://onlinelibrary.wiley.com/wol1/doi/10.1002/cpe.1422/fullpdf

Reference54 articles.

1. Handley M, Paxson V, Kreibich C. Network intrusion detection: Evasion, traffic normalization, and end-to-end protocol semantics. Proceedings of the 10th USENIX Security Symposium, Washington, DC, 2001.

2. Advanced Micro Devices. AMD Athlon 64 X2 Dual Core Processor. Available at: http://www.amd.com/us-en/Processors/ProductInformation/0,,30_118_9485_13041,00.html [20 November 2008].

3. Intel Corporation. Dual Core Intel Xeon Processor 7100 Sequence. Available at: http://www.intel.com/products/processor/xeon/7100_prodbrief.htm [20 November 2008].

4. Intel Corporation. Quad Core Intel Xeon Processor 5300 Sequence. Available at: ftp://download.intel.com/products/processor/xeon/dc53kprodbrief.pdf [20 November 2008].

5. Intel Corporation. Six Core Intel Xeon Processor. Available at: http://ark.intel.com/cpu.aspx?groupID=36937 [20 November 2008].

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