An 11-μ W, 9-bit fully differential, cyclic/algorithmic ADC in 0.13 μm CMOS-Reference-Cited by-同舟云学术

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An 11-μ W, 9-bit fully differential, cyclic/algorithmic ADC in 0.13 μm CMOS

Published:2016-11-15 Issue:8 Volume:45 Page:1095-1114
ISSN:0098-9886
Container-title:International Journal of Circuit Theory and Applications
language:en
Short-container-title:Int. J. Circ. Theor. Appl.

Author:

Bako Niko¹^ORCID,Fricke Kyle²,Sobot Robert²³,Baric Adrijan⁴

Affiliation:

1. Texas Instruments Deutschland; Haggertystasse 1 85356 Freising Germany

2. School of Electrical and Computer Engineering; Western University; London Ontario Canada

3. École Nationale Supérieure de l'Électronique et de ses Applications; University Cergy-Pontoise/CNRS; Cergy France

4. Faculty of Electrical Engineering and Computing; University of Zagreb; Zagreb Croatia

Funder

Mr. Ivo Broz

Publisher

Wiley

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Science Applications,Electronic, Optical and Magnetic Materials

Reference24 articles.

1. Far-field on-chip antennas monolithically integrated in a wireless-powered 5.8-GHz downlink/UWB uplink RFID tag in 0.18- μm standard CMOS;Radiom;IEEE Journal of Solid-State Circuits,2010

2. Fully integrated passive UHF RFID transponder IC with 16.7-μW minimum RF input power;Karthaus;IEEE Journal of Solid-State Circuits,2003

3. Remotely powered addressable UHF RFID integrated system;Curty;IEEE Journal of Solid-State Circuits,2005

4. A 21 fJ/conversion-step 100 kS/s 10-bit ADC with a low-noise time-domain comparator for low-power sensor interface;Lee;IEEE Journal of Solid-State Circuits,2011

5. An ultra low energy 12-bit rate-resolution scalable SAR ADC for wireless sensor nodes;Verma;IEEE Journal of Solid-State Circuits,2007

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Deterministic Digital Calibration Technique for 1.5 bits/stage Pipelined and Algorithmic ADCs with Finite op-amp Gain and Large Capacitance Mismatches;Circuits, Systems, and Signal Processing;2021-02-13

2. Low power 9-bit 500 kS/s 2-stage cyclic ADC using OTA variable bias current;Analog Integrated Circuits and Signal Processing;2020-08-04

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