1. Latchup
2. Transient-Induced Latchup in CMOS Integrated Circuits
3. Electrical Overstress (EOS)
4. Y. Huh K. Min P. Bendix V. Axelrad R. Narayan J.W. Chen L.D. Johnson S. Voldman Chip level layout and bias considerations for preventing neighboring I/O cell interaction-induced latchup and inter-power supply latchup in advanced CMOS technologies Proceedings of the Electrical Overstress/Electrostatic Discharge (EOS/ESD) Symposium 2005 100 107