Exploring one-sided communication and synchronization on a non-cache-coherent many-core architecture-Reference-Cited by-同舟云学术

Exploring one-sided communication and synchronization on a non-cache-coherent many-core architecture

Published:2017-03-29 Issue:15 Volume:29 Page:e4113
ISSN:1532-0626
Container-title:Concurrency and Computation: Practice and Experience
language:en
Short-container-title:Concurrency Computat.: Pract. Exper.

Author:

Christgau Steffen¹,Schnor Bettina¹

Affiliation:

1. Institute for Computer Science; University of Potsdam; August-Bebel-Strasse 89 Potsdam 14482 Germany

Publisher

Wiley

Subject

Computational Theory and Mathematics,Computer Networks and Communications,Computer Science Applications,Theoretical Computer Science,Software

Reference40 articles.

1. Morgan TP More Knights Landing Xeon Phi Secrets Unveiled 2015 http://www.nextplatform.com/2015/03/25/more-knights-landing-xeon-phi-secrets-unveiled/

2. Enabling highly-scalable remote memory access programming with MPI-3 one sided;Gerstenberger;Sci Program,2014

3. Problems with using MPI 1.1 and 2.0 as compilation targets for parallel language implementations;Bonachea;IJHPCN,2004

4. Howard J et al. A 48-core IA-32 message-passing processor with DVFS in 45nm CMOS Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International San Francisco, CA, USA San Francisco, CA, USA 2010 108 109

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