High isolation and high power of 0.13 µm CMOS SPDT switch using deep‐N‐well transistors and floating‐body technique in K‐band

Abstract

AbstractA K‐band high isolation single‐pole double‐throw (SPDT) switch using a 0.13 µm CMOS process is presented. Two on‐state resistors of shunt Deep‐N‐Well (DNW) transistors are used to improve isolation. The floating‐body technique is utilized to enhance the power‐handling capability. The off‐state capacitors of two DNW transistors are employed to construct an impedance‐matching network. The switch achieves a measured insertion loss of 3.0–3.2 dB and an isolation of better than 35 dB from 17 to 27 GHz. A measured input 1 dB compression power (IP1dB) of 11.8 dBm is obtained at 24 GHz. The chip size of the proposed switch is 0.52 × 0.66 mm2 with a core area of only 0.33 × 0.27 mm2.