13.2: Equalizer and Clock/Data Recovery Circuits in SDICs for Intra‐Panel Interface
Author:
Affiliation:
1. Department of Research and Development New Vision Microelectronics, Inc. Building of No. 31, 680 Guiping Road Shanghai China
Publisher
Wiley
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1002/sdtp.13410
Reference16 articles.
1. A 2.0 Gb/s Clock-Embedded Interface for Full-HD 10-Bit 120 Hz LCD Drivers With 1/5-Rate Noise-Tolerant Phase and Frequency Recovery
2. An Input Data and Power Noise Inducing Clock Jitter Tolerant Reference-Less Digital CDR for LCD Intra-Panel Interface;Kim Y.H.;IEEE Transactions on Circuits and Systems: I Regular papers,2017
3. 840-Mb/s CMOS demultiplexed equalizing transceiver for DRAM-to-Processor communication;Sim J.;Symp. VLSI Circuits Dig. Tech. Papers,1999
4. A 2.5 Gb/s adaptive cable equalizer;Shakiba M. H.;IEEE ISSCC Dig. Tech. Papers,1999
5. A 0.3-/spl mu/m CMOS 8-Gb/s 4-PAM serial link transceiver
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