Fast settling frequency synthesizer with two-point channel control paths

Author:

Shin Sangho,Kang Sung-Mo “Steve”

Publisher

Wiley

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Science Applications,Electronic, Optical and Magnetic Materials

Reference11 articles.

1. A 6.5-GHz energy-efficient BFSK modulator for wireless sensor applications;Cho;IEEE Journal of Solid-state Circuits,2004

2. Speeding up an integer-N PLL by controlling the loop filter charge;Hakkinen;IEEE Transactions on Circuits and Systems-II,2003

3. Design of CMOS adaptive-bandwidth PLL/DLLs: a general approach;Kim;IEEE Transactions on Circuits and Systems-II,2003

4. All-digital PLL with ultra fast settling;Staszewski;IEEE Transactions on Circuits and Systems-II,2007

5. Shin S Lee K Kang SM 4.2 mW CMOS frequency synthesizer for 2.4 GHz ZigBee application with fast settling time performance 411 414

Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A fast settling frequency synthesizer with switched‐bandwidth loop filter;International Journal of Circuit Theory and Applications;2021-03-19

2. A wideband low-spur 0.18-µm CMOS phase-locked loop with bandwidth calibration;International Journal of Circuit Theory and Applications;2015-05-06

3. Spur reduction in frequency synthesizer with an array of switched capacitors;International Journal of Circuit Theory and Applications;2014-10-30

4. Dynamics of charge-pump phase-locked loops;International Journal of Circuit Theory and Applications;2012-04-19

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