Positive‐to‐negative tunable delay circuit designed with NGD RC network

Author:

Junwen Shi1,Junyan Cui1,Silochi Hakim Epea1,Wieser Robert1,Galan Raul Sanchez2,Murad Nour Mohammad3ORCID,Ravelo Blaise1ORCID

Affiliation:

1. Nanjing University of Information Science & Technology (NUIST) Nanjing Jiangsu China

2. 4i Intelligent Insights, Tecnoincubadora Marie Curie, PCT Cartuja Sevilla Spain

3. PIMENT Lab, Network and Telecom Dpt, IUT of Saint Pierre University of La Reunion Reunion France

Abstract

SummaryDespite the performed progressive research work, the interpretation of the negative group delay (NGD) function remains not familiar to non‐specialist design and fabrication circuit engineers. The functionality misunderstanding limits the NGD circuit applications compared to other classical electronic functions. The present paper deals with the design of a tunable circuit by operating with positive and negative delay behaviors. The topology of the tunable circuit by using a low‐pass (LP) type NGD circuit is described. The design formulas for calculating the circuit resistor and capacitor parameters from the desired delay are expressed. The design feasibility of the tunable circuit composed of LP‐NGD cell and RC‐circuit is validated with a proof‐of‐concept (PoC) implemented on a test board. Two different signals with pulse and arbitrary waveforms having tens‐milliseconds duration were considered during the validation tests. As expected by tuning a varistor from 0.4 kΩ to 1 kΩ, the negative delay behavior varying from about −0.4 ms was verified thanks to the time‐advanced effect due to the LP‐NGD property. Then, the output signal delay was observed to become positive when the varistor was tuned from 1 kΩ to 3 kΩ.

Publisher

Wiley

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