Transistor size optimization in digital circuits using ant colony optimization for continuous domain

Author:

Gupta Himanshu1,Ghosh Bahniman1

Affiliation:

1. Indian Institute of Technology Kanpur; Department of Electrical Engineering; India

Publisher

Wiley

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Science Applications,Electronic, Optical and Magnetic Materials

Reference20 articles.

1. A new efficient SC integrator scheme for high-speed low-power applications;Amoroso;International Journal of Circuit Theory and Applications,2010

2. Power-delay optimization of D-latch/MUX source coupled logic gates;Alioto;International Journal of Circuit Theory and Applications,2005

3. An exact solution to the transistor sizing problem for CMOS circuits using convex optimization;Sapatnekar;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,1993

4. Analog circuit design by nonconvex polynomial optimization: Two design examples;Lui;International Journal of Circuit Theory and Applications,2010

5. Lecture Notes in Computer Science;Rogenmoser,1996

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