High‐Density Vertical Transistors with Pitch Size Down to 20 nm

Abstract

AbstractVertical field effect transistors (VFETs) have attracted considerable interest for developing ultra‐scaled devices. In particular, individual VFET can be stacked on top of another and does not consume additional chip footprint beyond what is needed for a single device at the bottom, representing another dimension for high‐density transistors. However, high‐density VFETs with small pitch size are difficult to fabricate and is largely limited by the trade‐offs between drain thickness and its conductivity. Here, a simple approach is reported to scale the drain to sub‐10 nm. By combining 7 nm thick Au with monolayer graphene, the hybrid drain demonstrates metallic behavior with low sheet resistance of ≈100 Ω sq−1. By van der Waals laminating the hybrid drain on top of 3 nm thick channel and scaling gate stack, the total VFET pitch size down to 20 nm and demonstrates a higher on‐state current of 730 A cm−2. Furthermore, three individual VFETs together are vertically stacked within a vertical distance of 59 nm, representing the record low pitch size for vertical transistors. The method pushes the scaling limit and pitch size limit of VFET, opening up a new pathway for high‐density vertical transistors and integrated circuits.