Introduction to Schottky-Barrier MOS Architectures: Concept, Challenges, Material Engineering and Device Integration

Author:

Dubois E.,Larrieu G.,Valentin R,Breil N.,Danneville F.

Publisher

John Wiley & Sons, Inc.

Reference100 articles.

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2. BARLAGE D. et al. “High-frequency response of 100-nm integrated CMOS transistors with high- k gate dielectrics” Electron Devices Meeting, IEDM Technical Digest. International 2001

3. “Selective etching of Pt with respect to PtSi using a sacrificial low temperature germanidation process”;BREIL;Appl. Phys. Lett.,2007

4. “Integration of PtSi in p-type MOSFETs using a sacrificial low-temperature germanidation process”;BREIL;IEEE Electron Device Letters,2008

5. “Formation of cobalt silicided shallow junction using implant into/through silicide technology and low temperature furnace annealing”;CHEN;IEEE Trans. Electron Devices,1996

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