Analog and linearity performance analysis of ferroelectric vertical tunnel field effect transistor with and without source pocket

Author:

Singh Ashish Kumar1,Kumar Ramesh1,Maity Heranmoy2,Singh Prabhat3ORCID,Singh Sarabdeep4ORCID

Affiliation:

1. Department of CSE Chitkara University Institute of Engineering and Technology, Chitkara University Chandigarh Punjab India

2. Deptartment of ECE Pailan College of Management and Technology Kolkata India

3. Department of ECE Dr. B.R. Ambedkar National Institute of Technology Jalandhar Punjab India

4. Department of ECE Model Institute of Engineering and Technology Jammu India

Abstract

AbstractThis study examines the electrical performance characteristics of a ferroelectric vertical tunnel field‐effect transistor (TFET) with and without a source pocket (Si0.5Ge0.5). The incorporation of Germanium in the source of the TFET aims to enhance the on‐current. The Silvaco TCAD simulation tool is utilized to simulate the proposed structure. To improve device performance, a ferroelectric layer with a vertical length is employed in the gate of the TFET. When the ferroelectric layer partially controls the channel region, device characteristics, such as on‐current and subthreshold swing (SS) can be improved (i.e., ION = 15.21 × 10−5 A/μm, ION/IOFF = 5.03 × 109, and a minimum SS of 20.87 mV/decade at 300 K). This article studied a comparison between ferroelectric vertical TFETs and nonferroelectric vertical TFETs, as well as ferroelectric vertical TFETs with and without source pockets. The comparison is done on the basis of DC and RF parameters. Analysis of this comparison represents that ferroelectric vertical TFET with source pocket has improved characteristics.

Publisher

Wiley

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