A low-chip area and low-phase noise hybrid phase-locked loop

Author:

Huang Jhin-Fang,Hsu Chien-Ming,Chen Kuo-Lung

Publisher

Wiley

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference10 articles.

1. Fast-lock hybrid PLL combining fractional-N and integer-N modes of differing bandwidths;Woo;IEEE J Solid-State Circuit,2008

2. A low-power frequency synthesizer with quadrature signal generation for 2.4 GHz zigbee transceiver applications;Srinivasan;IEEE Int. Symp. Circuits and Systems (ISCAS),2007

3. A low-power quadrature VCO and its application to a 0.6-V 2.4-GHz PLL;Lu;IEEE Trans Circuit Syst,2010

4. J.F. Huang Y.J. Jiangn R.Y. Liu The Gm-boosting VCO chip design for 5.8 GHz WiMAX applications 2010 443 445

5. A PLL clock generator with 5 to 110 MHz of lock range for microprocessors;Young;IEEE J Solid-State Circuits,1992

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