Parallel architectures for RLS with directional forgetting-Reference-Cited by-同舟云学术

Parallel architectures for RLS with directional forgetting

Published:1987-09 Issue:1 Volume:1 Page:69-88
ISSN:0890-6327
Container-title:International Journal of Adaptive Control and Signal Processing
language:en
Short-container-title:Int. J. Adapt. Control Signal Process.

Author:

Chisci L.,Mosca E.

Publisher

Wiley

Subject

Electrical and Electronic Engineering,Signal Processing,Control and Systems Engineering

Reference17 articles.

1. and , Dynamic System Identification, Academic Press, New York, 1977, pp. 179–185.

2. Implementation of self-tuning regulators with variable forgetting factors

3. ‘The problem of forgetting old data in recursive estimation’, Proc. IFAC Workshop on Adaptive Systems in Control and Signal Processing, San Francisco, CA, U.S.A., 1983.

4. and , ‘Tracking of slowly varying parameters by directional forgetting’, Proc. 9th IFAC World Congress, Budapest, Hungary, 1984, pp. 78–83.

5. and , ‘A prediction-error direcional forgetting technique for recursive estimation’, Proc. 4th Int. Conf. on System Engineering, Coventry, U.K., 1985, pp. 7–12.

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. An FPGA-based parallel architecture for on-line parameter estimation using the RLS identification algorithm;Microprocessors and Microsystems;2014-07

2. A systolic array for recursive least squares computations: mapping directionally weighted RLS on an SVD updating array;IEEE Transactions on Signal Processing;1996

3. Recursive least-square algorithm with ud factorization by fixed-point arithmetic;Electronics and Communications in Japan (Part III: Fundamental Electronic Science);1992-01

4. Floating-point error analysis for recursive least-square algorithm using ud factorization;Electronics and Communications in Japan (Part III: Fundamental Electronic Science);1991

5. Transputers for industrial applications;Concurrency: Practice and Experience;1989-12