Pseudo Split Gate In 0 . 53 Ga 0 .47 As/InP Hetero‐Junction Tunnel FET : Design and Analysis-Reference-Cited by-同舟云学术

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Pseudo Split Gate In 0 . 53 Ga 0 .47 As/InP Hetero‐Junction Tunnel FET : Design and Analysis

Published:2020-11-02 Issue:2 Volume:34 Page:
ISSN:0894-3370
Container-title:International Journal of Numerical Modelling: Electronic Networks, Devices and Fields
language:en
Short-container-title:Int J Numer Model

Author:

Haris Mohd¹,Loan Sajad A.¹^ORCID,Mainuddin ¹

Affiliation:

1. Department of Electronics and Communication Engineering Jamia Millia Islamia (Central University) New Delhi India

Publisher

Wiley

Subject

Electrical and Electronic Engineering,Computer Science Applications,Modeling and Simulation

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1002/jnm.2826

Reference43 articles.

1. Device scaling limits of Si MOSFETs and their application dependencies

2. M.Lundstrom “Device physics at the scaling limit: what matters? [mosfets].” Paper presented at: IEEE International Electron Devices Meeting2003 Dec2003 pp.33.1.1–33.1.4.

3. A Novel Partial-Ground-Plane-Based MOSFET on Selective Buried Oxide: 2-D Simulation Study

4. Tunnel field-effect transistors as energy-efficient electronic switches

5. Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec

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