Evaluating optimizations that reduce global memory accesses of stencil computations in GPGPUs-Reference-Cited by-同舟云学术

Evaluating optimizations that reduce global memory accesses of stencil computations in GPGPUs

Author:

Carrijo Nasciutti Thiago¹^ORCID,Panetta Jairo¹,Pais Lopes Pedro¹

Affiliation:

1. Divisão de Ciência da ComputaçãoInstituto Tecnológico de Aeronáutica (ITA) São José dos Campos, São Paulo Brazil

Funder

European Union's Horizon 2020 Programme

Brazilian Ministry of Science, Technology and Innovation through Rede Nacional de Pesquisa

Publisher

Wiley

Subject

Computational Theory and Mathematics,Computer Networks and Communications,Computer Science Applications,Theoretical Computer Science,Software

Link

Reference14 articles.

3. NVIDIA.Kepler GK110 Whitepaper.2012.http://www.nvidia.com/content/PDF/kepler/NVIDIA-Kepler-GK110-Architecture-Whitepaper.pdf

4. NVIDIA.CUDA C programming guide v8.0.2017.http://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html

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