1. Abusland AA Lande TS Høvin M 1996 A VLSI communication architecture for stochastically pulse-encoded analog signals. Proc. IEEE Int. Symp. Circuits Syst. (ISCAS) III 401 404
2. AER 1993 The address-event representation communcation protocol [sic], AER 0.02
3. Baker B Whatley AM 1997 Silicon cortex daughter board 1 http://www.ini.uzh.ch/amw/scx/daughter.htmlSCXDB1
4. Berge HKO Häfliger P. 2007 High-speed serial AER on FPGA. Proc. IEEE Int. Symp. Circuits Syst. (ISCAS) 857 860
5. A quantitative map of the circuit of cat primary visual cortex;Binzegger;J. Neurosci,2004