A Model of Wafer Warpage for Trench Field‐Plate Power MOSFETs

Abstract

A new wafer warpage model is proposed for the full process design of trench field‐plate (FP) power metal‐oxide‐semiconductor fileld‐effect transitors (MOSFETs) using large‐sized wafer. Trench FP power MOSFETs feature a deep trench and thick oxide at the wafer surface. Wafer warpage occurs due to the stress imbalance between the front and back sides of the wafer. This warpage leads to significant problems with transport errors in manufacturing equipment. This issue is expected to become even more crucial as lateral pitch narrowing is employed to reduce on‐resistance. In this study, two methods are compared to estimate the warpage of a 200 mm diameter Si‐wafer after trench etching and oxidation process. The mechanical stress generated by the oxidation process in several cell units is calculated using a 3D simulation. In the first approach, wafer warpage is converted from the displacement of the cell units. In the second approach, wafer warpage is estimated based on the surface film stress, which is calculated in the 3D simulation. The second approach shows good agreement with experimental results and is applicable to the 300 mm diameter Si process. This method yields more accurate measurements than the method using displacement.