A Generic Methodology for Breakdown Voltage Optimization of Lateral Silicon‐On‐Insulator Power Devices-Reference-Cited by-同舟云学术

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A Generic Methodology for Breakdown Voltage Optimization of Lateral Silicon‐On‐Insulator Power Devices

Published:2020-06-11 Issue:16 Volume:217 Page:2000042
ISSN:1862-6300
Container-title:physica status solidi (a)
language:en
Short-container-title:Phys. Status Solidi A

Author:

Kumar Viswanathan Naveen¹²^ORCID,Mudholkar Mihir²^ORCID,Quddus Mohammed Tanvir²

Affiliation:

1. Department of Electrical, Computer and Energy EngineeringArizona State University Tempe AZ 85287-5706 USA

2. Power Solutions GroupON Semiconductor 5005 E McDowell Road Phoenix AZ 85008 USA

Publisher

Wiley

Subject

Materials Chemistry,Electrical and Electronic Engineering,Surfaces, Coatings and Films,Surfaces and Interfaces,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1002/pssa.202000042

Reference11 articles.

1. Analysis and Optimization of the Back-Gate Effect on Lateral High-Voltage SOI Devices

2. Analytical Model and Optimization for Variable Drift Region Width SOI LDMOS Device

3. A novel high voltage lateral double diffused metal oxide semiconductor (LDMOS) device with a U-shaped buried oxide feature

4. S.Merchant E.Arnold H.Baumgart S.Mukherjee H.Pein R.Pinker inProc. of the 3rd Int. Symp. on Power Semiconductor Devices and ICs IEEE1991 pp.31–35.

5. Optimizing Design of Breakdown Voltage to Eliminate Back Gate Bias Effect in Silicon-on-Insulator Diode Using Low Doping Buried Layer

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