Affiliation:
1. Łukasiewicz Research Network – Institute of Microelectronics and Photonics Al. Lotników 32/46 Warsaw 02‐668 Poland
2. Warsaw University of Technology Institute of Microelectronics and Optoelectronics Koszykowa 75 Warsaw 00‐662 Poland
Abstract
One of the key elements of vertical high‐voltage GaN‐based devices is a properly designed junction termination extension (JTE) structure. One of the approaches to the fabrication of JTE structures is the use of p‐type epitaxial layers and their appropriate shaping to obtain high values of breakdown voltage. In this work, optimization of two‐zone (TZ) step‐etched JTE structures for vertical GaN power devices using technology computer aided design simulations is presented. Two constructions of the device are used, with a single‐zone (SZ‐JTE) and TZ‐JTE (TZ‐JTE) structure. The dependence of the breakdown voltage of SZ‐JTE structure is very sensitive to its thickness. The maximum breakdown voltage of 1654 V is obtained for the SZ‐JTE thickness of 110 nm. The use of a TZ‐JTE with an appropriate segment thickness ratio allows for a breakdown voltage above 75% of the theoretical value (≈1500 V) for a much wider range of JTE thicknesses and to achieve higher values of the breakdown voltage, reaching ≈96% of the theoretical value (1887 V). Finally, the performed simulations allow to map the full dependence on the thickness of the TZ‐JTE areas (2D‐map) and to determine the process window leading to the breakdown voltage above 1500 V.
Funder
Narodowe Centrum Badań i Rozwoju