Integrated CPU Monitoring Using 2D Temperature Sensor Arrays Directly Printed on Heat Sinks

Author:

Huber Robert1ORCID,Belles Daniel1,Bücher Tim2,Franke Leonard1,Amrouch Hussam23,Lemmer Uli14ORCID

Affiliation:

1. Light Technology Institute (LTI) Karlsruhe Institute for Technology (KIT) Engesserstrasse 13 76131 Karlsruhe Germany

2. Semiconductor Test and Reliability (STAR) University of Stuttgart Pfaffenwaldring 47 70569 Stuttgart Germany

3. Chair of AI Processor Design; Munich Institute of Robotics and Machine Intelligence Technical University Munich (TUM) Georg‐Brauchle‐Ring 60 80992 Munich Germany

4. Institute of Microstructure Technology (IMT) Karlsruhe Institute for Technology (KIT) Hermann‐von‐Helmholtz‐Platz 1 76344 Eggenstein‐Leopoldshafen Germany

Abstract

AbstractIn today's digital world, the demand for computer security and system reliability is a crucial element. Monitoring the CPU temperature during operation provides valuable insights but is currently limited to the embedded on‐chip sensors. The implementation of an extra security layer based on temperature monitoring can detect anomalies in an early stage, identify malware, and help mitigate attacks. The approach of integrating more on‐chip temperature sensors into the silicon is avoided due to space, power limitations, and cost constraints. However, the field of printed electronics and sensor technology has recently seen significant progress. This is the first work that introduces a fully‐printed temperature sensor array integrated onto the cooling unit of a CPU. It offers a novel approach for the practical implementation of such sensors into an operational computer system. The present sensor array, consisting of 396 sensor pixels, detects local hotspots induced by the underneath CPU cores, leading to an individual thermal fingerprint. This unique method paves the way for addressing pivotal elements of computer security, as deviations from expected thermal behavior can signal malicious activities. Additionally, this innovation facilitates reliability optimization. The detailed thermal map garnered provides insights into which cores are subjected to significant stress over time.

Funder

Deutsche Forschungsgemeinschaft

Publisher

Wiley

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