Junctionless Negative‐Differential‐Resistance Device Using 2D Van‐Der‐Waals Layered Materials for Ternary Parallel Computing

Author:

Lee Taeran1,Jung Kil‐Su23,Seo Seunghwan145,Lee Junseo1,Park Jihye6,Kang Sumin4,Park Jeongwon4,Kang Juncheol1,Ahn Hogeun1,Kim Suhyun1,Lee Hae Won7,Lee Doyoon58,Kim Ki Seok58,Kim Hyunseok58910,Heo Keun11,Kim Sunmean12,Bae Sang‐Hoon1314,Kang Seokhyeong6,Kang Kibum415,Kim Jeehwan58,Park Jin‐Hong1ORCID

Affiliation:

1. Department of Electrical and Computer Engineering Sungkyunkwan University (SKKU) Suwon 16419 South Korea

2. Flash Memory Technology Design Team Samsung Electronics Co. Ltd. Giheung 17113 South Korea

3. Department of Semiconductor and Display Engineering Sungkyunkwan University (SKKU) Suwon 16419 South Korea

4. Department of Materials Science and Engineering Korea Advanced Institute of Science and Technology (KAIST) Daejeon 34141 South Korea

5. Research Laboratory of Electronics Massachusetts Institute of Technology (MIT) Cambridge MA 02138 USA

6. Department of Electrical Engineering Pohang University of Science and Technology (POSTECH) Pohang 37673 South Korea

7. Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology (MIT) Cambridge MA 02138 USA

8. Department of Mechanical Engineering Massachusetts Institute of Technology (MIT) Cambridge MA 02138 USA

9. Department of Electrical and Computer Engineering University of Illinois Urbana‐Champaign (UIUC) Urbana IL 61801 USA

10. Nick Holonyak Jr. Micro and Nanotechnology Laboratory University of Illinois Urbana‐Champaign (UIUC) Urbana IL 61801 USA

11. School of Semiconductor Science & Technology Jeonbuk National University Jeonju 54896 South Korea

12. School of Electronics Engineering College of IT Engineering Kyungpook National University Daegu 41566 South Korea

13. Department of Mechanical Engineering and Materials Science Washington University in Saint Louis Missouri MO 63130 USA

14. Institute of Materials Science and Engineering Washington University in Saint Louis Missouri MO 63130 USA

15. Graduate School of Semiconductor Technology Korea Advanced Institute of Science and Technology (KAIST) Daejeon 34141 South Korea

Abstract

AbstractNegative‐differential‐resistance (NDR) devices offer a promising pathway for developing future computing technologies characterized by exceptionally low energy consumption, especially multivalued logic computing. Nevertheless, conventional approaches aimed at attaining the NDR phenomenon involve intricate junction configurations and/or external doping processes in the channel region, impeding the progress of NDR devices to the circuit and system levels. Here, an NDR device is presented that incorporates a channel without junctions. The NDR phenomenon is achieved by introducing a metal‐insulator‐semiconductor capacitor to a portion of the channel area. This approach establishes partial potential barrier and well that effectively restrict the movement of hole and electron carriers within specific voltage ranges. Consequently, this facilitates the implementation of both a ternary inverter and a ternary static‐random‐access‐memory, which are essential components in the development of multivalued logic computing technology.

Funder

National Research Foundation of Korea

Ministry of Trade, Industry and Energy

Publisher

Wiley

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