Wafer yield prediction using derived spatial variables

Author:

Dong Hang1,Chen Nan2,Wang Kaibo1

Affiliation:

1. Department of Industrial Engineering; Tsinghua University; Beijing China

2. Department of Industrial Systems Engineering and Management; National University of Singapore; Singapore

Funder

National Natural Science Foundation of China

Publisher

Wiley

Subject

Management Science and Operations Research,Safety, Risk, Reliability and Quality

Reference37 articles.

1. A dual burn-in policy for defect-tolerant memory products using the number of repairs as a quality indicator;Tong;Microelectron Reliab,2008

2. Development of a dual burn-in policy for semiconductor products based on the number of defective neighborhood chips;Tong;Int J Reliab Qual Saf Eng,2006

3. Mirza AI O'Donoghue G Drake AW Graves SC Spatial yield modeling for semiconductor wafers Cambridge, Massachusetts, USA 1995 276 281

4. Monitoring wafer map data from integrated circuit fabrication processes for spatially clustered defects;Hansen;Technometrics,1997

5. Statistical methods for visual defect metrology;Cunningham;IEEE Trans Semicond Manuf,1998

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