Boosting the 3D thermal-aware floorplanning problem through a master-worker parallel MOEA

Author:

Arnaldo Ignacio1,Cuesta-Infante Alfredo2,Manuel Colmenar J.2,Risco-Martín José L.1,Ayala José L.1

Affiliation:

1. DACYA; Complutense University of Madrid; Madrid; Spain

2. CES Felipe II; Complutense University of Madrid; Madrid, Aranjuez; Spain

Publisher

Wiley

Subject

Computational Theory and Mathematics,Computer Networks and Communications,Computer Science Applications,Theoretical Computer Science,Software

Reference24 articles.

1. Intel 2012 http://techresearch.intel.com/ProjectDetails.aspx?Id=1

2. 3D stacked microprocessor: Are we there yet?;Loh;Micro, IEEE,2010

3. Design challenges of technology scaling;Borkar;Micro, IEEE,1999

4. Srinivasan J Adve SV Bose P Rivers JA The impact of technology scaling on lifetime reliability Dependable Systems and Networks, 2004 International Conference On 2004 177 186 10.1109/DSN.2004.1311888

5. A case for thermal-aware floorplanning at the microarchitectural level;Sankaranarayanan;Journal of Instruction-Level Parallelism,2005

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