Efficient memory architecture for image processing-Reference-Cited by-同舟云学术

Efficient memory architecture for image processing

Published:2011-03 Issue:3 Volume:39 Page:351-356
ISSN:0098-9886
Container-title:International Journal of Circuit Theory and Applications
language:en
Short-container-title:Int. J. Circ. Theor. Appl.

Author:

Perri Stefania,Corsonello Pasquale

Publisher

Wiley

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Science Applications,Electronic, Optical and Magnetic Materials

Reference8 articles.

1. Design and implementation of optimized architecture for computing the 2D-DWT for JPEG2000 compression;Souani;International Journal of Circuit Theory and Applications,2009

2. An efficient paradigm for wavelet-based image processing using cellular neural networks;Yu;International Journal of Circuit Theory and Applications,2009

3. A five-stage pipeline, 204 cycles/ MB, single-port SRAM-based deblocking filter for H.264/AVC;Xu;IEEE Transactions on Circuits and Systems for Video Technology,2008

4. Gupta AK Nooshabadi S Taubman D Optimal 2 sub-bank memory architecture for Bit Plane Coder of JPEG2000 2005 4373 4376

5. Mingo FL Carrabina J A library of memory controllers for an image processing prototyping system 1998 188 193

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